The section describes the programming interface of the MCG Hal driver. More...

Enumerations
enum	_mcg_constant { kMcgConstant1 = (1u), kMcgConstant5 = (5u), kMcgConstant640 = (640u), kMcgConstant1280 = (1280u), kMcgConstant1920 = (1920u), kMcgConstant2560 = (2560u), kMcgConstant732 = (732u), kMcgConstant1464 = (1464u), kMcgConstant2197 = (2197u), kMcgConstant2929 = (2929u), kMcgConstantHex20 = (0x20u), kMcgConstantHex40 = (0x40u), kMcgConstantHex60 = (0x60u), kMcgConstantHex80 = (0x80u), kMcgConstantHexA0 = (0xA0u), kMcgConstantHexC0 = (0xC0u), kMcgConstantHexE0 = (0xE0u) }
	MCG constant definitions.

enum	mcg_clock_select_t { kMcgClockSelectOut, kMcgClockSelectIn, kMcgClockSelectExt, kMcgClockSelectReserved }
	MCG clock source select.

enum	mcg_iref_clock_source_t { kMcgIrefClockSourceExt, kMcgIrefClockSourceSlow }
	MCG internal reference clock source select.

enum	mcg_freq_range_select_t { kMcgFreqRangeSelectLow, kMcgFreqRangeSelectHigh, kMcgFreqRangeSelectVeryHigh, kMcgFreqRangeSelectVeryHigh1 }
	MCG frequency range select.

enum	mcg_hgo_select_t { kMcgHgoSelectLow, kMcgHgoSelectHigh }
	MCG high gain oscillator select.

enum	mcg_eref_clock_select_t { kMcgErefClockSelectExt, kMcgErefClockSelectOsc }
	MCG high gain oscillator select.

enum	mcg_lp_select_t { kMcgLpSelectNormal, kMcgLpSelectLowPower }
	MCG low power select.

enum	mcg_iref_clock_select_t { kMcgIrefClockSelectSlow, kMcgIrefClockSelectFast }
	MCG internal reference clock select.

enum	mcg_dmx32_select_t { kMcgDmx32Default, kMcgDmx32Fine }
	MCG DCO Maximum Frequency with 32.768 kHz Reference.

enum	mcg_dco_range_select_t { kMcgDcoRangeSelectLow, kMcgDcoRangeSelectMid, kMcgDcoRangeSelectMidHigh, kMcgDcoRangeSelectHigh }
	MCG DCO range select.

enum	mcg_pll_eref_clock_select_t { kMcgPllErefClockSelectOsc0, kMcgPllErefClockSelectOsc1 }
	MCG PLL external reference clock select.

enum	mcg_pll_select_t { kMcgPllSelectFll, kMcgPllSelectPllcs }
	MCG PLL select.

enum	mcg_lols_status_t { kMcgLolsNotLostLock, kMcgLolsLostLock }
	MCG loss of lock status.

enum	mcg_lock_status_t { kMcgLockUnlocked, kMcgLockLocked }
	MCG lock status.

enum	mcg_pllst_status_t { kMcgPllstFll, kMcgPllstPllcs }
	MCG clock status.

enum	mcg_irefst_status_t { kMcgIrefstExt, kMcgIrefstInt }
	MCG iref status.

enum	mcg_clkst_status_t { kMcgClkstFll, kMcgClkstIref, kMcgClkstEref, kMcgClkstPll }
	MCG clock mode status.

enum	mcg_ircst_status_t { kMcgIrcstSlow, kMcgIrcstFast }
	MCG ircst status.

enum	mcg_atmf_status_t { kMcgAtmfNormal, kMcgAtmfFail }
	MCG auto trim fail status.

enum	mcg_locs0_status_t { kMcgLocs0NotOccured, kMcgLocs0Occured }
	MCG loss of clock status.

enum	mcg_atms_select_t { kMcgAtmsSelect32k, kMcgAtmsSelect4m }
	MCG Automatic Trim Machine Select.

enum	mcg_oscsel_select_t { kMcgOscselOsc, kMcgOscselRtc, kMcgOscselIrc }
	MCG OSC Clock Select.

enum	mcg_locs1_status_t { kMcgLocs1NotOccured, kMcgLocs1Occured }
	MCG loss of clock status.

enum	mcg_pllcs_select_t { kMcgPllcsSelectPll0, kMcgPllcsSelectPll1 }
	MCG PLLCS select.

enum	mcg_locs2_status_t { kMcgLocs2NotOccured, kMcgLocs2Occured }
	MCG loss of clock status.

MCG out clock access API
uint32_t	clock_hal_get_fllclk (void)
	Gets the current MCG FLL clock. More...

uint32_t	clock_hal_get_pll0clk (void)
	Gets the current MCG PLL/PLL0 clock. More...

uint32_t	clock_hal_get_irclk (void)
	Gets the current MCG IR clock. More...

uint32_t	clock_hal_get_outclk (void)
	Gets the current MCG out clock. More...

MCG control register access API
static void	clock_set_clks (mcg_clock_select_t select)
	Sets the Clock Source Select. More...

static mcg_clock_select_t	clock_get_clks (void)
	Gets the Clock Source Select. More...

static void	clock_set_frdiv (uint8_t setting)
	Sets the FLL External Reference Divider. More...

static uint8_t	clock_get_frdiv (void)
	Gets the FLL External Reference Divider. More...

static void	clock_set_irefs (mcg_iref_clock_source_t select)
	Sets the Internal Reference Select. More...

static mcg_iref_clock_source_t	clock_get_irefs (void)
	Gets the Internal Reference Select. More...

static void	clock_set_clks_frdiv_irefs (mcg_clock_select_t clks, uint8_t frdiv, mcg_iref_clock_source_t irefs)
	Sets the CLKS, FRDIV and IREFS at the same time. More...

static void	clock_set_irclken (bool enable)
	Sets the Enable Internal Reference Clock setting. More...

static bool	clock_get_irclken (void)
	Gets the enable Internal Reference Clock setting. More...

static void	clock_set_irefsten (bool enable)
	Sets the Internal Reference Clock Stop Enable setting. More...

static bool	clock_get_irefsten (void)
	Gets the Enable Internal Reference Clock setting. More...

static void	clock_set_locre0 (bool enable)
	Sets the Loss of Clock Reset Enable setting. More...

static bool	clock_get_locre0 (void)
	Gets the Loss of Clock Reset Enable setting. More...

static void	clock_set_range0 (mcg_freq_range_select_t select)
	Sets the Frequency Range Select. More...

static mcg_freq_range_select_t	clock_get_range0 (void)
	Gets the Frequency Range Select. More...

static void	clock_set_hgo0 (mcg_hgo_select_t select)
	Sets the High Gain Oscillator Select. More...

static mcg_hgo_select_t	clock_get_hgo0 (void)
	Gets the High Gain Oscillator Select. More...

static void	clock_set_erefs0 (mcg_eref_clock_select_t select)
	Sets the External Reference Select. More...

static mcg_eref_clock_select_t	clock_get_erefs0 (void)
	Gets the External Reference Select. More...

static void	clock_set_lp (mcg_lp_select_t select)
	Sets the Low Power Select. More...

static mcg_lp_select_t	clock_get_lp (void)
	Gets the Low Power Select. More...

static void	clock_set_ircs (mcg_iref_clock_select_t select)
	Sets the Internal Reference Clock Select. More...

static mcg_iref_clock_select_t	clock_get_ircs (void)
	Gets the Internal Reference Clock Select. More...

static void	clock_set_sctrim (uint8_t setting)
	Sets the Slow Internal Reference Clock Trim Setting. More...

static uint8_t	clock_get_sctrim (void)
	Gets the Slow Internal Reference Clock Trim Setting. More...

static void	clock_set_dmx32 (mcg_dmx32_select_t setting)
	Sets the DCO Maximum Frequency with 32.768 kHz Reference. More...

static mcg_dmx32_select_t	clock_get_dmx32 (void)
	Gets the DCO Maximum Frequency with the 32.768 kHz Reference Setting. More...

static void	clock_set_drst_drs (mcg_dco_range_select_t setting)
	Sets the DCO Range Select. More...

static mcg_dco_range_select_t	clock_get_drst_drs (void)
	Gets the DCO Range Select Setting. More...

static void	clock_set_fctrim (uint8_t setting)
	Sets the Fast Internal Reference Clock Trim Setting. More...

static uint8_t	clock_get_fctrim (void)
	Gets the Fast Internal Reference Clock Trim Setting. More...

static void	clock_set_scftrim (uint8_t setting)
	Sets the Slow Internal Reference Clock Fine Trim Setting. More...

static uint8_t	clock_get_scftrim (void)
	Gets the Slow Internal Reference Clock Fine Trim Setting. More...

static void	clock_set_pllclken0 (bool enable)
	Sets the PLL Clock Enable Setting. More...

static bool	clock_get_pllclken0 (void)
	Gets the PLL Clock Enable Setting. More...

static void	clock_set_pllsten0 (bool enable)
	Sets the PLL0 Stop Enable Setting. More...

static bool	clock_get_pllsten0 (void)
	Gets the PLL0 Stop Enable Setting. More...

static void	clock_set_prdiv0 (uint8_t setting)
	Sets the PLL0 External Reference Divider Setting. More...

static uint8_t	clock_get_prdiv0 (void)
	Gets the PLL0 External Reference Divider Setting. More...

static void	clock_set_lolie0 (bool enable)
	Sets the Loss of Lock Interrupt Enable Setting. More...

static bool	clock_get_lolie0 (void)
	Gets the Loss of the Lock Interrupt Enable Setting. More...

static void	clock_set_plls (mcg_pll_select_t setting)
	Sets the PLL Select Setting. More...

static mcg_pll_select_t	clock_get_plls (void)
	Gets the PLL Select Setting. More...

static void	clock_set_cme0 (bool enable)
	Sets the Clock Monitor Enable Setting. More...

static bool	clock_get_cme0 (void)
	Gets the Clock Monitor Enable Setting. More...

static void	clock_set_vdiv0 (uint8_t setting)
	Sets the VCO0 Divider Setting. More...

static uint8_t	clock_get_vdiv0 (void)
	Gets the VCO0 Divider Setting. More...

static mcg_lols_status_t	clock_get_lols0 (void)
	Gets the Loss of the Lock Status. More...

static mcg_lock_status_t	clock_get_lock0 (void)
	Gets the Lock Status. More...

static mcg_pllst_status_t	clock_get_pllst (void)
	Gets the PLL Select Status. More...

static mcg_irefst_status_t	clock_get_irefst (void)
	Gets the Internal Reference Status. More...

static mcg_clkst_status_t	clock_get_clkst (void)
	Gets the Clock Mode Status. More...

static uint8_t	clock_get_oscinit0 (void)
	Gets the OSC Initialization Status. More...

static mcg_ircst_status_t	clock_get_ircst (void)
	Gets the Internal Reference Clock Status. More...

static mcg_atmf_status_t	clock_get_atmf (void)
	Gets the Automatic Trim machine Fail Flag. More...

static void	clock_set_atmf (void)
	Sets the Automatic Trim machine Fail Flag. More...

static mcg_locs0_status_t	clock_get_locs0 (void)
	Gets the OSC0 Loss of Clock Status. More...

static void	clock_set_atme (bool enable)
	Sets the Automatic Trim Machine Enable Setting. More...

static bool	clock_get_atme (void)
	Gets the Automatic Trim Machine Enable Setting. More...

static void	clock_set_atms (mcg_atms_select_t setting)
	Sets the Automatic Trim Machine Select Setting. More...

static mcg_atms_select_t	clock_get_atms (void)
	Gets the Automatic Trim Machine Select Setting. More...

static void	clock_set_fltprsrv (bool enable)
	Sets the FLL Filter Preserve Enable Setting. More...

static bool	clock_get_fltprsrv (void)
	Gets the FLL Filter Preserve Enable Setting. More...

static void	clock_set_fcrdiv (uint8_t setting)
	Sets the Fast Clock Internal Reference Divider Setting. More...

static uint8_t	clock_get_fcrdiv (void)
	Gets the Fast Clock Internal Reference Divider Setting. More...

static void	clock_set_atcvh (uint8_t setting)
	Sets the ATM Compare Value High Setting. More...

static uint8_t	clock_get_atcvh (void)
	Gets the ATM Compare Value High Setting. More...

static void	clock_set_atcvl (uint8_t setting)
	Sets the ATM Compare Value Low Setting. More...

static uint8_t	clock_get_atcvl (void)
	Gets the ATM Compare Value Low Setting. More...

MCG Hal Driver

Overview

The multipurpose clock generator (MCG) module provides a several clock source choices for the MCU. The MCG HAL provides a set of APIs to accessing these registers.

Get current default reference clock frequency

The MCG HAL provides a set of APIs dedicated to get the system default clock frequency. For example, MCG out clock, FLL clock, PLL clock, etc.Example to get a default system reference clock:

#include "mcg/hal/fsl_mcg_hal.h"
// return frequncy value for specified clock name
uint32_t frequency = 0;
// get the current system default reference clock frequncy
frequency = clock_hal_get_outclk();

Function Documentation

uint32_t clock_hal_get_fllclk ( void )

This function returns the mcgfllclk value in frequency(Hertz) based on the current MCG configurations and settings. FLL should be properly configured in order to get the valid value.

Parameters

none

Returns: value Frequency value in Hertz of the mcgpllclk.

uint32_t clock_hal_get_pll0clk ( void )

This function returns the mcgpllclk/mcgpll0 value in frequency(Hertz) based on the current MCG configurations and settings. PLL/PLL0 should be properly configured in order to get the valid value.

Parameters

none

Returns: value Frequency value in Hertz of the mcgpllclk or the mcgpll0clk.

uint32_t clock_hal_get_irclk ( void )

This function returns the mcgirclk value in frequency (Hertz) based on the current MCG configurations and settings. It does not check if the mcgirclk is enabled or not, just calculate and return the value.

Parameters

none

Returns: value Frequency value in Hertz of the mcgirclk.

uint32_t clock_hal_get_outclk ( void )

This function returns the mcgoutclk value in frequency (Hertz) based on the current MCG configurations and settings. The configuration should be properly done in order to get the valid value.

Parameters

none

Returns: value Frequency value in Hertz of mcgoutclk.

static void clock_set_clks ( mcg_clock_select_t select )

inlinestatic

This function selects the clock source for the MCGOUTCLK.

Parameters

select

Clock source selection

00: Output of FLL or PLLCS is selected(depends on PLLS control bit)
01: Internal reference clock is selected.
10: External reference clock is selected.
11: Reserved.

static mcg_clock_select_t clock_get_clks ( void )

inlinestatic

This function gets the select of the clock source for the MCGOUTCLK.

Returns: select Clock source selection

static void clock_set_frdiv ( uint8_t setting )

inlinestatic

This function sets the FLL External Reference Divider.

Parameters

setting Divider setting

static uint8_t clock_get_frdiv ( void )

inlinestatic

This function gets the FLL External Reference Divider.

Returns: setting Divider setting

static void clock_set_irefs ( mcg_iref_clock_source_t select )

inlinestatic

This function selects the reference clock source for the FLL.

Parameters

select

Clock source select

0: External reference clock is selected
1: The slow internal reference clock is selected

static mcg_iref_clock_source_t clock_get_irefs ( void )

inlinestatic

This function gets the reference clock source for the FLL.

Returns: select Clock source select

static void clock_set_clks_frdiv_irefs	(	mcg_clock_select_t	clks,
		uint8_t	frdiv,
		mcg_iref_clock_source_t	irefs
	)

inlinestatic

This function sets the CLKS, FRDIV, and IREFS settings at the same time in order keep the integrity of the clock switching.

Parameters

clks	Clock source select
frdiv	FLL external reference divider select
irefs	Internal reference select

static void clock_set_irclken ( bool enable )

inlinestatic

This function enables/disables the internal reference clock to use as the MCGIRCLK.

enable Enable or disable internal reference clock.

true: MCGIRCLK active
false: MCGIRCLK inactive

static bool clock_get_irclken ( void )

inlinestatic

This function gets the reference clock enable setting.

Returns: enabled True if the internal reference clock is enabled.

static void clock_set_irefsten ( bool enable )

inlinestatic

This function controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.

enable Enable or disable the internal reference clock stop setting.

true: Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
false: Internal reference clock is disabled in Stop mode

static bool clock_get_irefsten ( void )

inlinestatic

This function gets the Internal Reference Clock Stop Enable setting.

Returns: enabled True if internal reference clock stop is enabled.

static void clock_set_locre0 ( bool enable )

inlinestatic

This function determines whether an interrupt or a reset request is made following a loss of the OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set.

enable Loss of Clock Reset Enable setting

true: Generate a reset request on a loss of OSC0 external reference clock
false: Interrupt request is generated on a loss of OSC0 external reference clock

static bool clock_get_locre0 ( void )

inlinestatic

This function gets the Loss of Clock Reset Enable setting.

Returns: enabled True if Loss of Clock Reset is enabled.

static void clock_set_range0 ( mcg_freq_range_select_t select )

inlinestatic

This function selects the frequency range for the crystal oscillator or an external clock source. See the Oscillator (OSC) chapter for more details and the device data sheet for the frequency ranges used.

select Frequency Range Select

00: Low frequency range selected for the crystal oscillator
01: High frequency range selected for the crystal oscillator
1X: Very high frequency range selected for the crystal oscillator

static mcg_freq_range_select_t clock_get_range0 ( void )

inlinestatic

This function gets the Frequency Range Select.

Returns: select Frequency Range Select

static void clock_set_hgo0 ( mcg_hgo_select_t select )

inlinestatic

This function controls the crystal oscillator mode of operation. See the Oscillator (OSC) chapter for more details.

select High Gain Oscillator Select.

0: Configure crystal oscillator for low-power operation
1: Configure crystal oscillator for high-gain operation

static mcg_hgo_select_t clock_get_hgo0 ( void )

inlinestatic

This function gets the High Gain Oscillator Select.

Returns: select High Gain Oscillator Select

static void clock_set_erefs0 ( mcg_eref_clock_select_t select )

inlinestatic

This function selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details.

select External Reference Select

0: External reference clock requested
1: Oscillator requested

static mcg_eref_clock_select_t clock_get_erefs0 ( void )

inlinestatic

This function gets the External Reference Select.

Returns: select External Reference Select

static void clock_set_lp ( mcg_lp_select_t select )

inlinestatic

This function controls whether the FLL (or PLL) is disabled in the BLPI and the BLPE modes. In the FBE or the PBE modes, setting this bit to 1 transitions the MCG into the BLPE mode; in the FBI mode, setting this bit to 1 transitions the MCG into the BLPI mode. In any other MCG mode, the LP bit has no affect..

select Low Power Select

0: FLL (or PLL) is not disabled in bypass modes
1: FLL (or PLL) is disabled in bypass modes (lower power)

static mcg_lp_select_t clock_get_lp ( void )

inlinestatic

This function gets the Low Power Select.

Returns: select Low Power Select

static void clock_set_ircs ( mcg_iref_clock_select_t select )

inlinestatic

This function selects between the fast or slow internal reference clock source.

select Low Power Select

0: Slow internal reference clock selected.
1: Fast internal reference clock selected.

static mcg_iref_clock_select_t clock_get_ircs ( void )

inlinestatic

This function gets the Internal Reference Clock Select.

Returns: select Internal Reference Clock Select

static void clock_set_sctrim ( uint8_t setting )

inlinestatic

This function controls the slow internal reference clock frequency by controlling the slow internal reference clock period. The SCTRIM bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0). Increasing the binary value increases the period, and decreasing the value decreases the period. An additional fine trim bit is available in the C4 register as the SCFTRIM bit. Upon reset, this value is loaded with a factory trim value. If an SCTRIM value stored in non-volatile memory is to be used, it is the user's responsibility to copy that value from the non-volatile memory location to this register.

setting Slow Internal Reference Clock Trim Setting

static uint8_t clock_get_sctrim ( void )

inlinestatic

This function gets the Slow Internal Reference Clock Trim Setting.

Returns: setting Slow Internal Reference Clock Trim Setting

static void clock_set_dmx32 ( mcg_dmx32_select_t setting )

inlinestatic

This function controls whether or not the DCO frequency range is narrowed to its maximum frequency with a 32.768 kHz reference.

setting DCO Maximum Frequency with 32.768 kHz Reference Setting

0: DCO has a default range of 25%.
1: DCO is fine-tuned for maximum frequency with 32.768 kHz reference.

static mcg_dmx32_select_t clock_get_dmx32 ( void )

inlinestatic

This function gets the DCO Maximum Frequency with 32.768 kHz Reference Setting.

Returns: setting DCO Maximum Frequency with 32.768 kHz Reference Setting

static void clock_set_drst_drs ( mcg_dco_range_select_t setting )

inlinestatic

This function selects the frequency range for the FLL output, DCOOUT. When the LP bit is set, the writes to the DRS bits are ignored. The DRST read field indicates the current frequency range for the DCOOUT. The DRST field does not update immediately after a write to the DRS field due to internal synchronization between the clock domains. See the DCO Frequency Range table for more details.

setting DCO Range Select Setting

00: Low range (reset default).
01: Mid range.
10: Mid-high range.
11: High range.

static mcg_dco_range_select_t clock_get_drst_drs ( void )

inlinestatic

This function gets the DCO Range Select Setting.

Returns: setting DCO Range Select Setting

static void clock_set_fctrim ( uint8_t setting )

inlinestatic

This function controls the fast internal reference clock frequency by controlling the fast internal reference clock period. The FCTRIM bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0). Increasing the binary value increases the period, and decreasing the value decreases the period. If an FCTRIM[3:0] value stored in non-volatile memory is to be used, it is the user's responsibility to copy that value from the non-volatile memory location to this register.

setting Fast Internal Reference Clock Trim Setting.

static uint8_t clock_get_fctrim ( void )

inlinestatic

This function gets the Fast Internal Reference Clock Trim Setting.

Returns: setting Fast Internal Reference Clock Trim Setting

static void clock_set_scftrim ( uint8_t setting )

inlinestatic

This function controls the smallest adjustment of the slow internal reference clock frequency. Setting the SCFTRIM increases the period and clearing the SCFTRIM decreases the period by the smallest amount possible. If an SCFTRIM value, stored in non-volatile memory, is to be used, it is the user's responsibility to copy that value from the non-volatile memory location to this bit.

setting Slow Internal Reference Clock Fine Trim Setting

static uint8_t clock_get_scftrim ( void )

inlinestatic

This function gets the Slow Internal Reference Clock Fine Trim Setting.

Returns: setting Slow Internal Reference Clock Fine Trim Setting

static void clock_set_pllclken0 ( bool enable )

inlinestatic

This function enables/disables the PLL0 independent of the PLLS and enables the PLL0 clock to use as the MCGPLL0CLK and the MCGPLL0CLK2X. (PRDIV0 needs to be programmed to the correct divider to generate a PLL1 reference clock in a valid reference range prior to setting the PLLCLKEN0 bit). Setting PLLCLKEN0 enables the external oscillator selected by REFSEL if not already enabled. Whenever the PLL0 is being enabled with the PLLCLKEN0 bit, and the external oscillator is being used as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set.

enable PLL Clock Enable Setting

true: MCGPLL0CLK and MCGPLL0CLK2X are active
false: MCGPLL0CLK and MCGPLL0CLK2X are inactive

static bool clock_get_pllclken0 ( void )

inlinestatic

This function gets the PLL Clock Enable Setting.

Returns: enabled True if PLL0 PLL Clock is enabled.

static void clock_set_pllsten0 ( bool enable )

inlinestatic

This function enables/disables the PLL0 Clock during a Normal Stop (In Low Power Stop mode, the PLL0 clock gets disabled even if PLLSTEN0=1). In all other power modes, the PLLSTEN0 bit has no affect and does not enable the PLL0 Clock to run if it is written to 1.

enable PLL0 Stop Enable Setting

true: MCGPLL0CLK and MCGPLL0CLK2X are enabled if system is in Normal Stop mode.
false: MCGPLL0CLK and MCGPLL0CLK2X are disabled in any of the Stop modes.

static bool clock_get_pllsten0 ( void )

inlinestatic

This function gets the PLL0 Stop Enable Setting.

Returns: enabled True if the PLL0 Stop is enabled.

static void clock_set_prdiv0 ( uint8_t setting )

inlinestatic

This function selects the amount to divide down the external reference clock for the PLL0. The resulting frequency must be in a valid reference range. After the PLL0 is enabled, (by setting either PLLCLKEN0 or PLLS), the PRDIV0 value must not be changed when LOCK0 is zero.

setting PLL0 External Reference Divider Setting

static uint8_t clock_get_prdiv0 ( void )

inlinestatic

This function gets the PLL0 External Reference Divider Setting.

Returns: setting PLL0 External Reference Divider Setting

static void clock_set_lolie0 ( bool enable )

inlinestatic

This function determine whether an interrupt request is made following a loss of lock indication. This bit only has an effect when LOLS 0 is set.

enable Loss of Lock Interrupt Enable Setting

true: Generate an interrupt request on loss of lock.
false: No interrupt request is generated on loss of lock.

static bool clock_get_lolie0 ( void )

inlinestatic

This function gets the Loss of the Lock Interrupt Enable Setting.

Returns: enabled True if the Loss of Lock Interrupt is enabled.

static void clock_set_plls ( mcg_pll_select_t setting )

inlinestatic

This function controls whether the PLLCS or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN0 and PLLCLKEN1 is not set, the PLLCS output clock is disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.

setting PLL Select Setting

0: FLL is selected.
1: PLLCS output clock is selected (PRDIV0 bits of PLL in control need to be programmed to the correct divider to generate a PLL reference clock in the range of 1 - 32 MHz prior to setting the PLLS bit).

static mcg_pll_select_t clock_get_plls ( void )

inlinestatic

This function gets the PLL Select Setting.

Returns: setting PLL Select Setting

static void clock_set_cme0 ( bool enable )

inlinestatic

This function enables/disables the loss of clock monitoring circuit for the OSC0 external reference mux select. The LOCRE0 bit determines whether an interrupt or a reset request is generated following a loss of the OSC0 indication. The CME0 bit should only be set to a logic 1 when the MCG is in an operational mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Whenever the CME0 bit is set to a logic 1, the value of the RANGE0 bits in the C2 register should not be changed. CME0 bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur while in Stop mode. CME0 should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.

enable Clock Monitor Enable Setting

true: External clock monitor is enabled for OSC0.
false: External clock monitor is disabled for OSC0.

static bool clock_get_cme0 ( void )

inlinestatic

This function gets the Clock Monitor Enable Setting.

Returns: enabled True if Clock Monitor is enabled

static void clock_set_vdiv0 ( uint8_t setting )

inlinestatic

This function selects the amount to divide the VCO output of the PLL0. The VDIV0 bits establish the multiplication factor (M) applied to the reference clock frequency. After the PLL0 is enabled (by setting either PLLCLKEN0 or PLLS), the VDIV0 value must not be changed when LOCK0 is zero.

setting VCO0 Divider Setting

static uint8_t clock_get_vdiv0 ( void )

inlinestatic

This function gets the VCO0 Divider Setting.

Returns: setting VCO0 Divider Setting

static mcg_lols_status_t clock_get_lols0 ( void )

inlinestatic

This function gets the Loss of Lock Status. This bit is a sticky bit indicating the lock status for the PLL. LOLS 0 is set if after acquiring lock, the PLL output frequency has fallen outside the lock exit frequency tolerance, D unl . LOLIE 0 determines whether an interrupt request is made when LOLS 0 is set. This bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 to this bit has no effect.

Returns

status Loss of Lock Status

0: PLL has not lost lock since LOLS 0 was last cleared
1: PLL has lost lock since LOLS 0 was last cleared

static mcg_lock_status_t clock_get_lock0 ( void )

inlinestatic

This function gets the Lock Status. This bit indicates whether the PLL0 has acquired the lock. Lock detection is disabled when not operating in either the PBE or the PEE mode unless PLLCLKEN0=1 and the MCG is not configured in the BLPI or the BLPE mode. While the PLL0 clock is locking to the desired frequency, MCGPLL0CLK and MCGPLL0CLK2X are gated off until the LOCK0 bit gets asserted. If the lock status bit is set, changing the value of the PRDIV0[2:0] bits in the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay cleared until the PLL0 has reacquired the lock. The loss of the PLL0 reference clock also causes the LOCK0 bit to clear until the PLL0 has an entry into the LLS, VLPS, or a regular Stop with PLLSTEN0=0 also causes the lock status bit to clear and stay cleared until the stop mode is exited and the PLL0 has reacquired the lock. Any time the PLL0 is enabled and the LOCK0 bit is cleared, the MCGPLL0CLK and MCGPLL0CLK2X are gated off until the LOCK0 bit is reasserted.

Returns

status Lock Status

0: PLL is currently unlocked
1: PLL is currently locked

static mcg_pllst_status_t clock_get_pllst ( void )

inlinestatic

This function gets the PLL Select Status. This bit indicates the clock source selected by PLLS . The PLLST bit does not update immediately after a write to the PLLS bit due to the internal synchronization between the clock domains.

Returns

status PLL Select Status

0: Source of PLLS clock is FLL clock.
1: Source of PLLS clock is PLLCS output clock.

static mcg_irefst_status_t clock_get_irefst ( void )

inlinestatic

This function gets the Internal Reference Status. This bit indicates the current source for the FLL reference clock. The IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between the clock domains.

Returns

status Internal Reference Status

0: Source of FLL reference clock is the external reference clock.
1: Source of FLL reference clock is the internal reference clock.

static mcg_clkst_status_t clock_get_clkst ( void )

inlinestatic

This function gets the Clock Mode Status. These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains.

Returns

status Clock Mode Status

00: Output of the FLL is selected (reset default).
01: Internal reference clock is selected.
10: External reference clock is selected.
11: Output of the PLL is selected.

static uint8_t clock_get_oscinit0 ( void )

inlinestatic

This function gets the OSC Initialization Status. This bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed description for more information.

Returns: status OSC Initialization Status

static mcg_ircst_status_t clock_get_ircst ( void )

inlinestatic

This function gets the Internal Reference Clock Status. The IRCST bit indicates the current source for the internal reference clock select clock (IRCSCLK). The IRCST bit does not update immediately after a write to the IRCS bit due to the internal synchronization between clock domains. The IRCST bit is only updated if the internal reference clock is enabled, either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit.

Returns

status Internal Reference Clock Status

0: Source of internal reference clock is the slow clock (32 kHz IRC).
1: Source of internal reference clock is the fast clock (2 MHz IRC).

static mcg_atmf_status_t clock_get_atmf ( void )

inlinestatic

This function gets the Automatic Trim machine Fail Flag. This Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is enabled (ATME=1) and a write to the C1, C3, C4, and SC registers is detected or the MCG enters into any Stop mode. A write to ATMF clears the flag.

Returns

flag Automatic Trim machine Fail Flag

0: Automatic Trim Machine completed normally.
1: Automatic Trim Machine failed.

static void clock_set_atmf ( void )

inlinestatic

This function clears the ATMF flag.

static mcg_locs0_status_t clock_get_locs0 ( void )

inlinestatic

This function gets the OSC0 Loss of Clock Status. The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a logic 1 to it when set.

Returns

status OSC0 Loss of Clock Status

0: Loss of OSC0 has not occurred.
1: Loss of OSC0 has occurred.

static void clock_set_atme ( bool enable )

inlinestatic

This function enables/disables the Auto Trim Machine to start automatically trimming the selected Internal Reference Clock. ATME de-asserts after the Auto Trim Machine has completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears this bit.

enable Automatic Trim Machine Enable Setting

true: Auto Trim Machine enabled
false: Auto Trim Machine disabled

static bool clock_get_atme ( void )

inlinestatic

This function gets the Automatic Trim Machine Enable Setting.

Returns: enabled True if Automatic Trim Machine is enabled

static void clock_set_atms ( mcg_atms_select_t setting )

inlinestatic

This function selects the IRCS clock for Auto Trim Test.

setting Automatic Trim Machine Select Setting

0: 32 kHz Internal Reference Clock selected
1: 4 MHz Internal Reference Clock selected

static mcg_atms_select_t clock_get_atms ( void )

inlinestatic

This function gets the Automatic Trim Machine Select Setting.

Returns: setting Automatic Trim Machine Select Setting

static void clock_set_fltprsrv ( bool enable )

inlinestatic

This function sets the FLL Filter Preserve Enable. This bit prevents the FLL filter values from resetting allowing the FLL output frequency to remain the same during the clock mode changes where the FLL/DCO output is still valid. (Note: This requires that the FLL reference frequency remain the same as the value prior to the new clock mode switch. Otherwise, the FLL filter and the frequency values change.)

enable FLL Filter Preserve Enable Setting

true: FLL filter and FLL frequency retain their previous values during new clock mode change
false: FLL filter and FLL frequency will reset on changes to correct clock mode

static bool clock_get_fltprsrv ( void )

inlinestatic

This function gets the FLL Filter Preserve Enable Setting.

Returns: enabled True if FLL Filter Preserve is enabled.

static void clock_set_fcrdiv ( uint8_t setting )

inlinestatic

This function selects the amount to divide down the fast internal reference clock. The resulting frequency is in the range 31.25 kHz to 4 MHz. (Note: Changing the divider when the Fast IRC is enabled is not supported).

setting Fast Clock Internal Reference Divider Setting

static uint8_t clock_get_fcrdiv ( void )

inlinestatic

This function gets the Fast Clock Internal Reference Divider Setting.

Returns: setting Fast Clock Internal Reference Divider Setting

static void clock_set_atcvh ( uint8_t setting )

inlinestatic

This function sets the ATM compare value high setting. The values are used by the Auto Trim Machine to compare and adjust the Internal Reference trim values during the ATM SAR conversion.

setting ATM Compare Value High Setting

static uint8_t clock_get_atcvh ( void )

inlinestatic

This function gets the ATM Compare Value High Setting.

Returns: setting ATM Compare Value High Setting

static void clock_set_atcvl ( uint8_t setting )

inlinestatic

This function sets the ATM compare value low setting. The values are used by the Auto Trim Machine to compare and adjust Internal Reference trim values during the ATM SAR conversion.

setting ATM Compare Value Low Setting

static uint8_t clock_get_atcvl ( void )

inlinestatic

This function gets the ATM Compare Value Low Setting.

Returns: setting ATM Compare Value Low Setting

Enumerations

MCG out clock access API

MCG control register access API

MCG Hal Driver

Overview

Get current default reference clock frequency

Function Documentation